The present invention relates generally to testing of IC (integrated circuit) dies during manufacture of IC (integrated circuit) packages, and more particularly, to a method and system for automatically determining and displaying the physical location of a failed cell of an array of memory cells on magnified images of a memory IC (integrated circuit) die having the array of memory cells.
Referring to FIG. 1, a memory IC (integrated circuit) die has a memory device fabricated therein such as a non-volatile flash memory device comprised of an array of flash memory cells 20, as known to one of ordinary skill in the art of electronics. In FIG. 1, a first flash memory cell 22 and a second flash memory cell 24 form a first row of flash memory cells, and a third flash memory cell 26 and a fourth flash memory cell 28 form a second row of flash memory cells. The first flash memory cell 22 and the third flash memory cell 26 form a first column of flash memory cells, and the second flash memory cell 24 and the fourth flash memory cell 28 form a second column of flash memory cells.
An array of memory cells for a typical non-volatile memory device has more numerous flash memory cells (such as millions of flash memory cells) with more numerous rows and columns of flash memory cells. However, four memory cells 22, 24, 26, and 28 in an array of two rows by two columns are illustrated in FIG. 1 for clarity of illustration.
Referring to FIG. 2, a cross sectional view 100 is shown of one of the flash memory cells 22, 24, 26, and 28. A flash memory cell is a floating gate MOS (metal oxide semiconductor) type of device for a non-volatile flash memory device, as known to one of ordinary skill in the art of electronics. The cross section 100 of a flash memory cell includes a control gate 102 which typically is comprised of polysilicon. A drain junction 104 that is doped with a junction dopant, such as arsenic (As) or phosphorous (P) for example, is formed within a semiconductor substrate 106. A source junction 108 that is doped with the junction dopant is formed within the semiconductor substrate 106.
A control dielectric structure is formed over a control gate area 110 within the semiconductor substrate 106 that is disposed between the drain junction 104 and the source junction 108. The control dielectric structure is comprised of a stack of a first dielectric layer 112 disposed on the semiconductor substrate 106, a second dielectric layer 114 disposed on the first dielectric layer 112, and a third dielectric layer 116 disposed on the second dielectric layer 114. In one example of the control dielectric structure, the first dielectric layer 112 is comprised of silicon dioxide (SiO2), the second dielectric layer 114 is comprised of silicon nitride (SiN), and the third dielectric layer 116 is comprised of silicon dioxide (SiO2). A first field oxide 118 is formed within the drain junction 104, and a second field oxide 120 is formed within the source junction 108 for electrically isolating the gate dielectric structure comprised of the first, second, and third dielectric layers 112, 114, and 116 and the control gate 102.
Referring to FIGS. 1 and 2, the drain junction of each of the memory cells in a column are coupled together to form a xe2x80x9cbit-linexe2x80x9d, as known to one of ordinary skill in the art of electronics. In FIG. 1, the first column of memory cells 22 and 26 are coupled to a first bit-line 32, and the second column of memory cells 24 and 28 are coupled to a second bit-line 34, for example. The control gate of each of the memory cells in a row are coupled together to form a xe2x80x9cword-linexe2x80x9d, as known to one of ordinary skill in the art of electronics. In FIG. 1, the first row of memory cells 22 and 24 are coupled to a first word-line 42, and the second row of memory cells 26 and 28 are coupled to a second word-line 44, for example.
Referring to FIG. 2, during a program operation or an erase operation of a cell of a flash memory device, charge carriers are injected into or injected out of the second dielectric layer 114. Such variation of the amount of charge carriers within the second dielectric layer 114 alters the threshold voltage of the control gate 102, as known to one of ordinary skill in the art of electronics. For example, when electrons are the charge carriers that are injected into the second dielectric layer 114, the threshold voltage increases. Alternatively, when electrons are the charge carriers that are injected out of the second dielectric layer 114, the threshold voltage decreases.
The charge carriers are injected into or injected out of the second dielectric layer 114 from the drain junction 104 to the control dielectric structure when bias voltages are applied on the control gate 102 via a control gate terminal 122 (i.e., the word-line coupled to the control gate 102), as known to one of ordinary skill in the art of electronics. For example, when a bias voltage of approximately +12V is applied on the control gate terminal 122 for programming the memory cell, electrons are injected into the second dielectric layer 114 from the drain junction 104 by hot carrier injection effect, as known to one of ordinary skill in the art of electronics. Alternatively, when a bias voltage of approximately xe2x88x9212V is applied on the control gate terminal 122 for erasing the memory cell, electrons are injected out of the second dielectric layer 114 and to the drain junction 104 by hot carrier injection effect, as known to one of ordinary skill in the art of electronics.
For reading digital bit information from a memory cell, a gate-to-source voltage of approximately 5.0V and a drain-to-source voltage of approximately 1.5V are applied to the memory cell. With such bias, the memory cell conducts current or does not conduct current depending on whether the memory cell has been programmed or erased. These two conditions are used as the two states for storing digital bit information within the flash memory cell 100, as known to one of ordinary skill in the art of electronics.
During manufacture of a non-volatile flash memory device, the memory IC die for the non-volatile flash memory device is tested for proper functionality. Systems for testing the functionality of the memory IC dies are known to one of ordinary skill in the art of IC package manufacture. Such a testing system outputs label information of a failed memory cell that does not function properly during such testing for indicating the physical location of such a failed memory cell on the memory IC die.
Label information for a memory IC die is devised during layout of the integrated circuit of the memory IC die, and such label information is recorded in a design book, as known to one of ordinary skill in the art of integrated circuit design. For example, referring to FIG. 3, an array of memory cells are fabricated in a memory IC die 202. The memory IC die 202 of FIG. 3 includes a plurality of contact pads 204, 206, 208, 210, 212, 214, 216, 218, 220, and 222 for providing connection to nodes of the flash memory integrated circuit fabricated on the IC die 202. A typical memory IC die includes more numerous contact pads, but ten contact pads 204, 206, 208, 210, 212, 214, 216, 218, 220, and 222 are illustrated in FIG. 3 for clarity of illustration.
Further referring to FIG. 3, the array of memory cells are divided into a plurality of sectors, including a first sector 232, a second sector 234, a third sector 236, and a fourth sector 238, on the memory IC die 202. A typical memory IC die includes more numerous sectors, but four sectors 232, 234, 236, and 238 are illustrated in FIG. 3 for clarity of illustration. The reason for designing the memory IC die 202 with a plurality of sectors is that during layout of the memory IC die 202, the layout for each sector may be stamped for easier layout of the memory IC die 202, as known to one of ordinary skill in the art of integrated circuit design. Thus, each of the sectors 232, 234, 236, and 238 on the memory IC die 202 have substantially identical layout.
Referring to FIGS. 3 and 4, each sector has a respective array of memory cells fabricated therein. Referring to FIG. 4, the first sector 232 for example includes a plurality of rows and a plurality of columns of memory cells. Referring to FIG. 1, the control gate of each memory cell in a row of memory cells is coupled to a word-line for that row. Referring to FIG. 4, a word-line for a row of memory cells is formed by a horizontal conductive structure including a first horizontal conductive structure 242, a second horizontal conductive structure 244, a third horizontal conductive structure 246, and a fourth horizontal conductive structure 248.
A horizontal conductive structure may be comprised of polysilicon for example when the horizontal conductive structure forms a word-line coupled to the control gate of each memory cell in a row of memory cells. A sector typically has more numerous horizontal conductive structures such as thousands of horizontal conductive structures for a higher number of rows of memory cells. However, four horizontal conductive structures 242, 244, 246, and 248 are shown in FIG. 4 for clarity of illustration.
Similarly, referring to FIG. 1, the drain of each memory cell in a column of memory cells is coupled to a bit-line for that column. An example vertical conductive structure 250 is referred to in FIG. 4 (but the other vertical conductive structures in FIG. 4 are not labeled with a number label for clarity of illustration). A vertical conductive structure typically is a metal line, as known to one of ordinary skill in the art of integrated circuit design.
A sector is typically comprised of a higher number of vertical conductive structures than illustrated in FIG. 4 (such as thousands of vertical conductive structures), but fewer vertical conductive structures are illustrated in FIG. 4 for clarity of illustration. The sector 232 is typically divided into a plurality of I/O regions including a first I/O region 262, a second I/O region 264, a third I/O region 266, and a fourth I/O region 268 (shown within dashed lines in FIG. 4). Each I/O region has a set pattern of vertical conductive structures therein. A typical sector 232 has more numerous I/O regions for more numerous vertical conductive structures in a sector, but four I/O regions 262, 264, 266, and 268 are illustrated in FIG. 4 for clarity of illustration. In addition, a typical I/O region has more numerous vertical conductive structures than illustrated in FIG. 4, but six vertical conductive structures are illustrated within each I/O region in FIG. 4 for clarity of illustration.
The reason for designing the sector 232 with a plurality of I/O regions is that during layout of the memory IC die 202, the layout for each I/O region may be stamped for easier layout of the memory IC die 202, as known to one of ordinary skill in the art of integrated circuit design. Thus, each of the I/O regions 262, 264, 266, and 268 have substantially identical layout. In addition, at least one vertical conductive structure is fabricated as a xe2x80x9credundancy regionxe2x80x9d between two adjacent I/O regions such that the adjacent I/O regions are visually distinct from each other. For example, in FIG. 4, a first vertical conductive structure 272 forms a first redundancy region disposed between the first I/O region 262 and the second I/O region 264, a second vertical conductive structure 274 forms a second redundancy region disposed between the second I/O region 264 and the third I/O region 266, and a third vertical conductive structure 276 forms a third redundancy region disposed between the third I/O region 266 and the fourth I/O region 268.
During testing of a memory IC die having an array of memory cells, a test station indicates the physical location of a failed memory cell by outputting a sector label, an I/O label, a row label, and a column label of the failed memory cell. Referring to FIG. 3, the sector label refers to one of the sectors 232, 234, 236, and 238 having the failed memory cell located therein. Referring to FIG. 4, the I/O label refers to one of the I/O regions 262, 264, 266 and 268 having the failed memory cell located therein within the sector corresponding to the sector label. The column label refers to one of the vertical conductive structures coupled to the drain of the failed memory cell within the I/O region corresponding to the I/O label. The row label indicates one of the horizontal conductive structures 242, 244, 246, and 248 coupled to the control gate of the failed memory cell.
When the test station determines the label information, including the sector label, the I/O label, the row label, and the column label of a failed memory cell, an operator locates the horizontal conductive structure and the vertical conductive structure coupled to such a failed memory cell to determine the physical location of the failed memory cell on the memory IC die. Further testing may be performed on the failed memory cell with determination of the location of the horizontal conductive structure and of the vertical conductive structure corresponding to the failed memory cell and of the physical location of the failed memory cell on the memory IC die to further determine the cause of failure of the memory cell. With determination of the cause of failure of the memory cell, corrective action may be undertaken to prevent the occurrence of failed memory cells during manufacture of memory IC dies.
In the prior art, when a test station outputs the label information of a sector label, an I/O label, a row label, and a column label of the failed memory cell, the operator studies the design book of how the memory IC die has been laid out to translate the label information to the physical location of the failed memory cell on the memory IC die. The operator views a magnified image of the memory IC die and counts the horizontal conductive structures and the vertical conductive structures to manually translate the label information of a sector label, an I/O label, a row label, and a column label of the failed memory cell to the physical location of the failed memory cell on the memory IC die.
Such a manual determination of the physical location of the failed memory cell requires the operator to count thousands of horizontal conductive structures and vertical conductive structures. As a result, manual determination of the physical location of the failed memory cell in the prior art is time consuming and is prone to human error.
Thus, a mechanism is desired for automatically determining and displaying the physical location of a failed memory cell of an array of memory cells on magnified images of a memory IC (integrated circuit) die.
Accordingly, in a general aspect of the present invention, a software application is used with a computer system for automatically determining and displaying the physical location of a failed memory cell of an array of memory cells on magnified images of a memory IC (integrated circuit) die from label information of the failed memory cell generated by a test station.
In a general aspect of the present invention, a data processor of the computer system accepts a memory IC (integrated circuit) die name corresponding to the memory IC die. The data processor also accepts a sector label. The memory IC die is comprised of a plurality of sectors, and the failed cell is located within a sector corresponding to the sector label. The data processor retrieves a first magnified image of the memory IC die corresponding to the memory IC die name from a data storage unit. The data processor maps the sector label to a sector corresponding to the sector label on the first magnified image of the memory IC die and may display the first magnified image of the memory IC die with the sector corresponding to the sector label highlighted on a GUI (graphical user interface).
In another embodiment of the present invention, the data processor accepts an I/O (input/output) label. The sector corresponding to the sector label is comprised of a plurality of I/O (input/output) regions, and the failed cell is located within an I/O region corresponding to the I/O label. The data processor retrieves a second magnified image of the sector corresponding to the sector label from the data storage unit. The data processor maps the I/O label to an I/O region corresponding to the I/O label on the second magnified image of the sector corresponding to the sector label, and displays the second magnified image of the sector corresponding to the sector label with the I/O region corresponding to the I/O label highlighted, on the GUI (graphical user interface).
In a further embodiment of the present invention, the data processor accepts a column label. The I/O region corresponding to the I/O label is comprised of a plurality of columns of memory cells. Each column of memory cells has a vertical conductive structure coupled to a node of each of the plurality of memory cells in the column, and the failed cell is located within a column of memory cells corresponding to the column label. The data processor retrieves a third magnified image of the I/O region corresponding to the I/O label from the data storage unit. The data processor maps the column label to a vertical conductive structure corresponding to the column label on the third magnified image of the I/O region corresponding to the I/O label and displays the third magnified image of the I/O region corresponding to the I/O label with the vertical conductive structure corresponding to the column label highlighted, on the GUI (graphical user interface).
In another embodiment of the present invention, the data processor accepts a row label. The I/O region corresponding to the I/O label is comprised of a plurality of rows of memory cells, and each row of memory cells has a horizontal conductive structure coupled to a node of each of the plurality of memory cells in the row. The failed cell is located within a row of memory cells corresponding to the row label. The data processor retrieves the third magnified image of the I/O region corresponding to the I/O label from the data storage unit. The data processor maps the row label to a horizontal conductive structure corresponding to the row label on the third magnified image of the I/O region corresponding to the I/O label and displays the third magnified image of the I/O region corresponding to the I/O label with the horizontal conductive structure corresponding to the row label highlighted, on the GUI (graphical user interface).
The present invention may be used to particular advantage when the memory IC die is a non-volatile flash memory device comprised of an array of floating gate MOS (metal oxide semiconductor) memory cells. In that case, the horizontal conductive structure may be a polysilicon line that is coupled to a control gate of each of a row of floating gate MOS memory cells, and the vertical conductive structure may be a metal line that is coupled to a drain of each of a column of floating gate MOS memory cells.
In this manner, the physical location of the horizontal conductive structure and of the vertical conductive structure and of the failed memory cell on magnified images of the memory IC die is automatically determined and displayed on the GUI (graphical user interface) from the label information of the failed memory cell within a relatively short period of time (such as a fraction of a minute, for example). Thus, an operator is saved from the time-consuming labor of counting thousands of conductive structures of the prior art manual determination process. In addition, the present invention avoids the human error of the prior art manual determination process.
These and other features and advantages of the present invention will be better understood by considering the following detailed description of the invention which is presented with the attached drawings.